1. Field of the Invention
The invention relates to an amplifying circuit, and more particularly to a switching amplifying circuit having a calibration operation to reduce output voltage offset.
2. Description of the Related Art
A DC voltage offset is defined by a non-zero DC voltage which is observed at an output terminal of the amplifier when a zero DC voltage is provided to an input terminal of the amplifier. In other words, DC voltage offset occurs in the amplifier. In general, most analog amplifiers, such as linear amplifiers and switching amplifiers, may suffer from DC voltage offset. An amplifier with DC voltage offset within a system may induce disadvantageous influences on some operations of the system. For example, in an audio system, if an amplifier has DC voltage within the audio system, when the audio system has operational state changes like entering or leavings a muted state, the DC voltage offset may induce unpleasant perceptible click/pop noises from a speaker of the audio system, degrading sound quality of the audio system.
Thus, it is desired to provide an amplifying circuit which can reduce DC voltage offset occurring in the amplifying system.